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Reduced instruction set computer
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41	23rd November 1993 Support Group Application Note Number: 202 Issue: 1.03CS Author: James Bye Add to Reading List Source URL: chrisacorns.computinghistory.org.uk Language: English - Date: 2013-08-13 09:33:18 Computer hardware Application directory RISC OS Acorn Archimedes BBC Micro Econet Reduced instruction set computing Operating system ARM architecture Acorn Computers Computing Computer architecture
42	SGI UV: Masaryk University Case Study ® University Benefits from Incredibly Fast Database Access and Built-In Redundancy Add to Reading List Source URL: is.muni.cz Language: English - Date: 2012-05-18 08:18:49 Silicon Graphics Software Altix Instruction set architectures NUMAlink Itanium Oracle Database Reduced instruction set computing Server Computing Computer architecture Supercomputers
43	Lecture 2: Review of Instruction Sets, Pipelines, and Caches Prof. David A. Patterson Computer Science 252 Spring 1998 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 1998-01-23 01:21:21 Instruction set PowerPC Reduced instruction set computing Processor register IBM 700/7000 series Computer architecture Central processing unit Computer hardware
44	Lecture 23: Goodbyte to Computer Architecture, Future Predictions, and Your Cal Cultural Heritage Professor David A. Patterson Computer Science 252 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 1998-05-08 14:16:37 Central processing unit Parallel computing Classes of computers Microprocessors Superscalar X86 Very long instruction word Instruction-level parallelism Reduced instruction set computing Computer architecture Computer hardware Computing
45	Bluespec Extensible RISC Implementation: BERI Hardware reference Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2015-04-14 11:22:52 Instruction set architectures Bluespec Inc. MIPS architecture Hardware description language Instruction set R4000 64-bit Reduced instruction set computing X86 debug register Computer architecture Computing Computer hardware
46	MIPS R5000 Microprocessor Technical Backgrounder Performance: SPECint95 Add to Reading List Source URL: www.sgidepot.co.uk Language: English - Date: 2008-04-15 15:08:30 MIPS architecture Central processing unit R4000 R4600 R8000 CPU cache R10000 R2000 Reduced instruction set computing Computer hardware Computer architecture R5000
47	SuperH™ (SH) 32-Bit RISC MCU/MPU Series SH7750 High-Performance RISC Engine Programming Manual Add to Reading List Source URL: mc.pp.se Language: English - Date: 1999-12-02 19:29:57 Central processing unit Instruction set architectures Virtual memory Computer memory Memory management unit SuperH CPU cache Reduced instruction set computing Addressing mode Computer architecture Computer hardware Computing
48	MIPS R5000 Microprocessor Technical Backgrounder Performance: SPECint95 Add to Reading List Source URL: vintagecomputers.info Language: English - Date: 1999-05-17 08:56:29 MIPS architecture Central processing unit R4000 R4600 R8000 CPU cache R10000 R2000 Reduced instruction set computing Computer hardware Computer architecture R5000
49	TM SuperH (SH) 64-Bit RISC Series SH-5 CPU Core, Volume 4: Add to Reading List Source URL: lars.nocrew.org Language: English Computer hardware Microcontrollers SuperH Central processing unit Reduced instruction set computing Undefined behavior Processor register Comparison of CPU architectures Computer architecture Computing Instruction set architectures
50	Hot Chips 15 Janus – A Gigaflop RISC + VLIW SoC Tile Pier S. PAOLUCCI a,b,, Ben ALTIERI a, Federico AGLIETTI a, Stefano V. BASILE a, Piergiovanni BAZZANA a, Sergio BRUZZONE a, Alessandro CATASTA a, Antonio CERRUTO a, Add to Reading List Source URL: www.hotchips.org Language: English* - Date: 2013-08-12 00:06:24 Parallel computing Very long instruction word Reduced instruction set computing Instruction set Digital signal processing Digital signal processors Computer architecture Computing Computer hardware

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